Careers

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

5+ years of relevant experience

Job Description:

• Be a member of the team that plays a significant role in ensuring the quality of next generation processors for Smart phones and Smart card through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include Interfacing with the design teams to ensure DFT design rules and guidelines are met.
• Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques. MBIST verification and test pattern generation through Mentor tool.
• Work closely with design team on IDDQ constrains validation and pattern generation along with IVA analysis.
• Simulating and verifying the ATPG (SAF, TDF) and MBIST patterns on unit delay and min/max timing corners.
• Working with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE debug.
• Lead team of 2-3 engineers working bin DFT/ADFT pattern generation and validation
• Contribute to technical innovation, development of innovative techniques in the area of test cost reduction, simulation time reduction and quality enhancement
• Responsible for supporting post Si debug effort, issue resolution
• Developing, enhancing and maintaining scripts as necessary.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

5+ years of relevant experience

Job Description:

• Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
• Requirement is MDs should have worked on nodes less than 7nm (n5 , n3 preferred)
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
• Experience of Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC,DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration,Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
• Ability to understand design constraints and implement high-quality layouts.
• Excellent command and problem-solving skills in over Physical layout verification.
• Multiple Tape out support experience will be an added advantage.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

5+ years of relevant experience

Job Description:

• Physical design process from floorplan till GDS generation.
• Skill sets - signoff like STA, PV, EM/IR, Scripting skills in Perl/Tcl/Python.
• Experience in latest sub-micron technologies below 10 nm.
• Hands–on experience in leading PnR tools Synopsys/Cadence.
• Experience in low-power designs and handling congestion or timing critical tiles will be preferred.
• Experience in ECO implementation preferred.
• Should be able to lead and mentor a team.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

5+ years of relevant experience

Job Description:

• Must have good knowledge on the verification flows.
• Experience in debug skills and problem-solving attitude.
• Complex test-bench/model in Verilog, System Verilog or SystemC.
• Working on Functional Verification, SoC Verification, Emulation.
• Good in programming: System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language.
• OVM/UVM Methodology knowledge and experience.
• Must have good communication skills and the ability to work in a team environment.
• Preferably having experience in architecture such as x86 or ARM domain-based SOCs.
• having SOC/IP performance verification background is added plus.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

8- 12 years of relevant experience

Job Description:

• Be a member of the team that plays a significant role in ensuring the quality of next generation processors for Smart phones and Smart card through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include Interfacing with the design teams to ensure DFT design rules and guidelines are met.
• Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques. MBIST verification and test pattern generation through Mentor tool.
• Work closely with design team on IDDQ constrains validation and pattern generation along with IVA analysis.
• Simulating and verifying the ATPG (SAF, TDF) and MBIST patterns on unit delay and min/max timing corners.
• Working with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE debug.
• Lead team of 2-3 engineers working bin DFT/ADFT pattern generation and validation
• Contribute to technical innovation, development of innovative techniques in the area of test cost reduction, simulation time reduction and quality enhancement
• Responsible for supporting post Si debug effort, issue resolution
• Developing, enhancing and maintaining scripts as necessary.

Skills:

• Minimum of 8 -12 year experience in ASIC/DFT and various aspects simulation, Silicon validation
• Detailed knowledge on DFT concepts, pattern simulation, Silicon debug
• In depth knowledge and hands on experience in ATPG, coverage analysis, Transition delay test coverage analysis.
• In-depth knowledge and hands on experience in Silicon debug, yield optimization
• Expertise in test mode timing constraints definition, Hands on experience with prime time is an added advantage
• Expertise in scripting languages such as perl, shell, etc. is an added advantage
• Knowledge/experience in post Si debug support
• Experience in simulating test vectors
• Working experience in System Verilog, Vera, modelsim tools
• Ability to work in an international team, dynamic environment
• Ability to learn and adapt to new tools and methodologies.
• Ability to do multi-tasking & work on several high priority designs in parallel.
• Past experience or ability to manage team
• Excellent problem solving skills
• Excellent communication and team work skills Experience with test tools such as Tetramax, Logic vision, Modelsim is highly desirable.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University.

Experience:

4 - 8 years of relevant experience

Key Responsibilities:

• Define the DFT Architecture for the next generation SoCs.
• Implementation & verification including Scan, MBIST, JTAG and other DFT’s related logic.
• Define and develop methodology for DFT insertion, pattern development, manufacturing tests, verifications, etc
• Working closely with cross functional teams to develop and verify DFT’s structures and constraints.
• Perform RTL and gate level (no-timing and timing) simulations to verify DFT functionality.
• Work closely with Test Engineering for test program development and Silicon bring up, diagnosis, Yield improvement, etc.
• Work closely with EDA RnD teams to propose and implement new features.

Requirements:

• B. Tech /BE/ME/M Tech with 4-8+ years of relevant hands-on experience in Design for Test (DFT).
• Clear understanding of key DFT concepts like Scan compression, Scan Stitching, fault models (stuck-at, delay tests, IDDQ, Small Delay, etc.), IEEE P1500, MBIST, IEEE 1149.1/6 (Boundary scan), IEEE 1687, etc.
• Working knowledge of RTL coding in Verilog, Synthesis & STA
• Experience in at least one scripting language like PERL, Python, TCL, or Shell.
• Hands on experience with either Tessent/TetraMax/Modus ATPG tool
• Hands-on experienced and successful taped out several ASICs.
• Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.
• Excellent written and verbal communication skills.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

5-7 years of relevant experience

Job Description:

• You will be responsible for IP / sub-system level micro-architecture development and RTL coding.
• Prepare block/sub-system level timing constraints.
• Integrate IP/sub-system.
• Perform basic verification either in IP Verification environment or FPGA.
• Deep knowledge of mixed signal concepts
• Deep knowledge of RTL design fundamentals
• Deep knowledge of Verilog and System-Verilog
• Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA)
• Write design specifications for different functional blocks on a chip, Create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and place and route to meet timing / area goals
• Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan efforts
• Code Verilog RTL for high performance designs
• Specify, design, and synthesize RTL blocks, optimize and floorplan them

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

5 - 8 years of relevant experience

Job Description:

• The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
• The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power.
• Must have experience in Cadence/Synopsys EDA Tools.
• Undertake full-chip flat / block level database timing analysis and provide budgets or suggestions to Sub-system and Block owners for convergence.
• Hands-on experience in STA of large blocks/Sub-systems or/and full chip
• Expert user of industry standard tools for timing signoff especially Synopsys PT.
• Expert in scripting languages (shell, perl, tcl) and Make flow.
• In-depth knowledge of 7nm/5nm/3nm technologies and associated physical design challenges.
• Should be self-motivated and take initiatives to drive new methodologies.
• Should have strong written and verbal communication skills.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

5 - 10 years of relevant experience

Job Description:

• You will be responsible for IP / sub-system level micro-architecture development and RTL coding.
• Prepare block/sub-system level timing constraints.
• Integrate IP/sub-system.
• Perform basic verification either in IP Verification environment or FPGA.
• Deep knowledge of mixed signal concepts
• Deep knowledge of RTL design fundamentals
• Deep knowledge of Verilog and System-Verilog
• Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA)
• Write design specifications for different functional blocks on a chip, create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and place and route to meet timing / area goals.
• Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan efforts.
• Code Verilog RTL for high performance designs
• Specify, design, and synthesize RTL blocks, optimize and floorplan them.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

7 - 10 years of relevant experience

Job Description:

• STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.
• Timing analysis, validation and debugging across multiple PVT conditions using PT/Tempus.
• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
• Evaluate multiple timing methodologies/tools on different designs and technology nodes.
• Work on automation scripts within STA/PD tools for methodology development.
• Good Technical writing and Communication skills,
• should be willing to work in cross-collaborative environment.
• Experience in design automation using TCL/Perl/Python.
• Familiar with digital flow design implementation RTL to GDS: ICC, Innovous , PT/Tempus
• Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

4 - 6 years of relevant experience

Job Description:

• Work with floorplan and physical design engineers to drive physical verification convergence.
•  Should be proficient in DRC and LVS analysis at advanced nodes like 5nm or below.
•  Good knowledge in specific areas like Antenna, ESD, ERC, LUP will be preferred.
• Working knowledge on full chip phyV will be added advantage.
• Prior work experience on FullChip RDL like IO/PADRing routing will be preferred.
•   Understanding multi voltage regions will be preferred.

Tools:

•  Expertise in Calibre/ICV and ICC2 tools.
• Scripting will be preferred.
• Scripting inside Calibre tool will be added asset.
• Automation [tcl, perl, python, etc,..]
• RDL experience
• Full chip/ subsystem LV experience in layout debug and fix
• Good PV-PD knowledge

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

3 - 8 years of relevant experience

Job Description:

• Experienced in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
• Should have hands on experience of Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
• Ability to understand design constraints and implement high-quality layouts.
• Excellent command and problem-solving skills in over Physical layout verification.
• Multiple Tape out support experience will be an added advantage.
• Scripting and automation experience is good to have but not mandatory.
• Excellent verbal and written communication skills.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

4 - 8 years of relevant experience

Job Description:

• In depth knowledge of DFT concepts, hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
• In depth knowledge and hands on experience in LBIST insertion
• Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.
• Expertise in scripting languages such as perl, shell, phython etc.
• Experience in RTL and Gate level & Power aware simulations of scan and MBIST test vectors
• Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (Tessent)

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

5 - 8 years of relevant experience

Job Description:

• Experience in the verification of IP cores.
• Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage.
• Experience on DDR Protocol is necessary. Understanding BIST would be an added advantage.
• Familiarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirable. Good communication skills, debug and problem-solving skills, mentoring teammates and should be self-motivated.
• Be a technical contributor in the Verification Tasks – System Verilog/Verilog coding of testbenches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM.
• Creates deliverables which do not require close review or supervision by a Senior Technical Engineer.
• Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs.

Qualification:

B.Tech / M.Tech or equivalent from a reputed University

Experience:

5 - 8 years of relevant experience

Job Description:

• Good development experience in C and data structure
• Experienced in device driver development for PMIC, Charging, I2C, USB-PD, BLE, GPIO, SPI, UART, JTAG, one wire etc.
• Working Experience on STM32 cube/Atmel based MCU or similar.
• Experience in hands-on design, development and troubleshooting on embedded targets
• Requires a solid understanding of the software development and project management life cycle.

Additional Skills:

• Excellent debugging & troubleshooting skills
• Sharp coding & designing skills
• Good communications skills and ability to work with both internal and external customers with wide range of knowledge and skill levels
• Should be able to work independently